Vector–Logic Synthesis of Deductive Matrices for Fault Simulation

The main idea is to create vector-logic computing that uses only read-write transactions on address memory process large data. task implement new simple and reliable models methods of vector based primitive in the technology flexible interpretive simulation digital system faults. Vector-logic a computational over bits binary functionality, where input data addresses bits. A method for synthesis deductive matrices transporting fault lists proposed, which has quadratic complexity. development algorithm truth table. matrix intended verification tests using parallel faults, as addresses, transaction cells memory.